Do you think Intel or AMD might use these

[dreplogle]

I'm wondering if Intel or AMD might use a similar process to design their CPU's. This seems like the way to go rather than have a bunch of engineers look at a schematic and say 'We'll, what if we do this, what will happen':cheers:

[michaelgarvie]

Intel and AMD are increasingly interested in concurrent checking circuits such as these. Traditionally they use Automatic Test Equipment which feeds test patterns into the chips and then analyses their response to check for faults. This off-line testing usually incurrs lower overhead on the chip itself. However as die density increases its harder and harder to get to every single wire and test it. Moreover chips will be increasingly susceptible to soft (transient) errors due to radiation making transistors flip from 1 to 0 for nanoseconds. All this makes concurrent checking (which is checking constantly during the chips operation) techniques such as these, not only attractive for their classical purpose as mission critical circuitry protection devices, but also attractive for massively produced high density chips for which we want an acceptable error rate.

AMD has been known to introduce some concurrent checking into their chips. And these are widely used in critical applications such as flight-control, anti-brake blocking, space applications, medical...